This invention relates to a semiconductor device, more particularly, a semiconductor device of the type wherein one of the electrodes is formed on a polycrystalline silicon body extending upwardly from a semiconductor substrate and a method of manufacturing the same.
In the manufacture of various semiconductor device, such as transistors and integrated circuits improvement of fine and highly accurate working technique has been strongly desired for the purpose of improving their characteristics. Especially, for improving the high frequency characteristics of bipolar silicon transistors for use in ultra high frequencies it is necessary to provide near construction and working technique for increasing the cutoff frequency and decreasing the base resistance and the collector-base junction capacitance.
However, in the prior art transistor of this type since the emitter, base and collector electrodes are formed on the same plane it is usual to install these electrodes at a spacing of about one micron for the purpose of electrically insulating them from each other. It has been recognized that when the spacing is made smaller, the transistor can be operated at higher frequencies. However, such spacing is limited by the accuracy of a photomask.
More particularly, among the problems regarding the photomask are included (a) the dimensional accuracy of a device pattern formed on a photomask, (b) the pitch accuracy of the device pattern formed on the photomask and (c) the accuracy of alignment between the device pattern already formed on a semiconductor wafer and device pattern of the photomask to be subsequently used. For this reason, when designing a photomask it is necessary to prepare the photomask having ample dimensions of the device pattern which permit respective errors in the accuracies described above. Where a device pattern having a small allowancce for the alignment of the semiconductor wafer and the photomask is used with sacrifice of the yield, and the alignment is made carefully with a sufficient time, the chance of contaminating and damaging the semiconductor wafer increases and the characteristics of the resulting semiconductor device are degraded.
Furthermore, the working of metal films which are used to form electrodes also affects fine and highly accurate working. More particularly, in order to obtain an electrode having a large current capacity the electrode should have a correspondingly larger cross-sectional area so that where the pattern width is limited due to design consideration, the thickness of the metal film to be worked becomes thick. When a thick metal film is etched a remarkable undercut appears thus making it difficult to attain the desired high accuracy of working.
Even when a skilled engineer carefully works there are errors of about .+-.0.2 micron in the dimension of the device pattern on the photomask, about .+-.0.3 micron in the device pattern pitch, and about .+-.0.3 micron in the alignment, namely an error of total of about .+-.0.8 micron. In addition, it is neccessary to take into consideration errors in the dimensions of the device pattern on the photomask, a photoresist pattern which is formed by baking the device pattern on the photoresist film and then developing, and a pattern formed by etching the substrate of the mask by using the photoresist pattern. In this manner, when photoetching technique is used to obtain products having dimensions of the order of microns it is inevitable to accompany dimensional errors.
In the case of an integrated circuit, lead wires for interconnecting various electrodes should be arranged on a plane with insulating spacings therebetween or in multilayers with insulator layers interposed therebetween.
For the purpose of improving the characteristics of the integrated circuit it has been proposed to dispose in the longitudinal direction one of the electrodes which have been arranged in the same plane with respect to other electrodes thereby eliminating the spacing between electrodes as disclosed in Japanese patent publication No. 16312, 1976, and U.S. patent application Ser. No. 706,596 filed on July 19, 1976 by Sakai, for example. The invention described in these applications will be described hereunder with reference to FIGS. 1A and 1B.
FIG. 1A shows the electrode construction of a transistor of the Japanese patent publication wherein an emitter electrode 12a is formed on a peak shaped polycrystalline silicon body 11a whereas FIG. 1B shows the electrode construction of a transistor of the U.S. patent application wherein an emitter electrode 12b is formed on a polycrystalline silicon body of an inverted frustum shape. These transistors having polycrystalline silicon bodies of the peak or inverted frustum shape are characterized in that the polycrystalline silicon bodies are used to form diffused emitter layers 13a and 13b that the width W.sub.1 of the upper surface can be made to be larger than the width W.sub.2 at the lower end of the polycrystalline silicon body at which it contacts the silicon substrate and that base electrodes 14a and 14b are formed by utilizing the difference in the widths (W.sub.1 -W.sub.2). If desired, base contact diffusion can also be made. In FIGS. 1A and 1B, 15a and 15b shown diffused base regions and 16a and 16b diffused collector regions.
With the constructions shown in FIGS. 1A and 1B, the positional relationship between the emitter electrodes 12a and 12b and the base electrodes 14a and 14b of the transistors is determined by the shape (peak and inverted frustum) of the polycrystalline silicon bodies so that the high frequency characteristic of the transistor can be improved.
Where such electrode construction is applied to the gate electrode of a MOS transistor it is possible to assure self-alignment of the source and drain electrodes. Also in the integrated circuit it becomes possible to form, at a high density, inside wirings and resistor elements without using interlead insulating layers.
However, such advantages can be realized in the transistors of the type described above only by shaping the sectional configuration of the polycrystalline silicon body to have accurate peak or inverted frustum shape. Accordingly, it is necessary to etch the polycrystalline silicon bodies to have accurate sectional configuration. In the construction shown in FIG. 1A, when the position of the photoresist pattern, not shown, that determines the position of the polycrystalline silicon body 11a differs slightly from the position of the diffused emitter layer 13a a nonuniform current distribution or a short circuit between the emitter and base electrodes would be resulted thus degrading the characteristics of the transistor. In the construction shown in FIG. 1B, unless the difference between W.sub.1 and W.sub.2 is made substantial the isolation between the emitter electrode 12b and the base electrode 14b becomes difficult thus causing short circuiting or leakage of the current.
Considering these problems in more detail, the inverted frustum is formed by utilizing the variation in the etching speed which is different depending upon the concentration of the impurities contained in the polycrystalline silicon body. With a chemical etching method it is difficult to independently control the amount of etching in the horizontal and vertical direction. Consequently, if the amount of etching is not sufficient at the inclined side surface of the inverted frustum short circuiting between the emitter and base electrodes would be resulted. On the other hand, if the amount of etching of these portions were too large the area of the emitter electrode would become too small, thus limiting the current capacity. Furthermore, in the constructions shown in FIGS. 1A and 1B it is impossible to make sufficiently large the thickness of the emitter electrode, since if the thickness of the emitter electrode were too large, for example 0.3 micron and more, the spacing between the base and emitter electrodes would become two small thus causing short circuiting. For this reason, with this construction it is impossible to obtain transistors having a large current capacity (that is emitter electrode having a large sectional area).